Input buffers that convert a conventional 5 volt swing to differential Diode Load Emitter Coupled Logic (ECL) levels are known. One known input buffer is illustrated in FIG. 1. The input buffer includes an input circuit 10, a differential amplifier 12, and a bias circuit 14. The input circuit includes a plurality of series coupled diodes 70, 72, and 74, which, when implemented on an integrated circuit (IC), are formed by bipolar transistors having their collector and base terminals coupled together. The first transistor (diode) 70 has its collector and base coupled to a V.sub.CC bias source, and its emitter coupled to the collector and base of transistor (diode) 72, which is similarly coupled to transistor 74. A resistor 76, which is typically a high valued resistor having a large area on the integrated circuit, is coupled between the emitter of transistor (diode) 74 and the base and collector of a transistor 78, which is also connected as a diode. The logic input to the buffer is applied at an input 30 and coupled to the emitter of transistor (diode) 78. An input 32, of the differential amplifier 12, is also coupled to the junction of resistor 76 and diode 78. It will be understood that when the input signal at the buffer input 30 is high, a high input is applied at the differential amplifier's input 32, and when the input signal at input 30 is low, a low input is applied to input 32. During the time that the input 30 is low, current will flow through the diodes 70, 72, and 74, resistor 76, and diode 78. The circuit, therefore, continually draws current while at a low input state. This, of course, is wasteful use of power.
The differential amplifier input 32 is applied to the base of a first differential transistor 34. Its emitter is coupled to an emitter of a second differential transistor 36, both of which are coupled to the collector of a transistor 38, which serves as a current source with its emitter coupled to ground. A plurality of transistors 40, 42, and 44 are coupled as series coupled diodes between the V.sub.CC supply and the collector of transistor 34, while a similar series of transistors 46, 48 and 50, also coupled as diodes, are coupled between the V.sub.CC supply and the collector of a transistor 36. An output 52 of the buffer, is provided by a connection to the collector of the transistor 36, while an inverted output 54 is provided by a connection to the collector of the transistor 34. The bias circuit 14 includes a resistor 56 coupled between V.sub.CC and the base of a transistor 36. Two transistors 58 and 60 are series coupled as diodes between the junction of resistor 56 and transistor 36, and ground. The junction of diodes, 58 and 60 is coupled to the base of transistor 38 to control the current through the transistor 38.
In operation, when a low signal is applied to the input 30, the base of transistor 34 is pulled low and the transistor 34 is turned off, which produces a high output at the inverter output 54. Conversely, when the transistor 36 is turned on, a low output is provided at the buffer output 52. When a high input signal is applied to the input 30, the transistor 34 is turned on causing transistor 36 to switch off, which provides a high output signal at buffer output 52, and low output signal at inverter buffer output 54.
Accordingly, since the input buffer wastes power when receiving a logic low, a need exists for an input buffer that minimizes this waste in power, while maintaining a high speed of operation.